in 1 in 2 d 1 d 2 s 1 s 2 v v+ gnd nc s 4 s 3 d 4 d 3 in 4 in 3 dual-in-line and soic 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 top view s 1 nc s 2 in 3 v d 3 v+ d 4 nc in 4 nc nc gnd in 2 nc d 2 s 4 d 1 s 3 in 1 key top view lcc 910111213 4 5 6 7 8 1 2 319 20 14 15 16 17 18 dg201a dg201a dg201a/202 siliconix s-52880erev. e, 28-apr-97 1 monolithic quad spst cmos analog switches features benefits applications 15-v input range low off leakageei d(on) : 0.1 na low on-resistanceer ds(on) : 115 44-v maximum supply ratings ttl and cmos compatible wide input range low distortion switching can be driven from comparators or op amps without limiting resistors disk drives radar systems communications systems sample-and-hold description the dg201a and dg202 are quad spst analog switches designed to provide accurate switching over a wide range of input signals. when combining a low on-resistance and a wide signal range ( 15 v) with low charge-transfer these devices are well suited for industrial and military applications. built on siliconix' high voltage metal gate process to achieve optimum switch performance, each switch conducts equally well in both directions when on. when off these switches will block up to 30 v peak-to-peak and have a 44-v absolute maximum power supply rating. these two devices are differentiated by the type of switch actions (see truth table). the dg201b/dg202b upgrades are recommended for new designs. functional block diagram and pin configuration truth table logic dg201a dg202 0 on off 1 off on logic a0o 0.8 v logic a1o 2.4 v updates to this data sheet may be obtained via facsimile by calling siliconix faxback, 1-408-970-5600. please request faxback document #70036.
dg201a/202 2 siliconix s-52880erev. e, 28-apr-97 ordering information temp range package part number 0to70 c 16 pin plastic dip dg201acj 0 to 70 c 16 - pin plastic dip dg202cj 25 to 85 c 16-pin cerdip dg201abk 40 to 85 c 16-pin narrow soic dg201ady dg201aak dg201aak/883, jm38510/12302bea 55 to 125 c 16-pin cerdip 7705301ea dg202ak dg202ak/883 16 pin sidebraze jm38510/12302bec 55 to 125 c 16 - pin sidebraze 7705301ec lcc-20 77053012a absolute maximum ratings voltages referenced to v v+ 44 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd 25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital inputs a v s , v d (v) 2 v to (v+) +2 v . . . . . . . . . . . . . . . . . . or 20 ma, whichever occurs first current, any terminal except s or d 30 ma . . . . . . . . . . . . . . . . . . . . continuous current, s or d 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . peak current, s or d (pulsed at 1 ms, 10% duty cycle max) 70 ma . . . . . . . . . . . . . . . . . . . . storage temperature (k, z suffix) 65 to 150 c . . . . . . . . . . . (j, y suffix) 65 to 125 c . . . . . . . . . . . power dissipation (package)b 16-pin plastic dip c 470 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-pin soic d 640 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-pin cerdip and sidebraze e 900 mw . . . . . . . . . . . . . . . . . . . . . . . . lcc-20 f 750 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes: a. signals on s x , d x , or in x exceeding v+ or v will be clamped by internal diodes. limit forward diode current to maximum current ratings. b. all leads welded or soldered to pc board. c. derate 6.5 mw/ c above 25 c d. derate 7.6 mw/ c above 75 c e. derate 12 mw/ c above 75 c f. derate 10 mw/ c above 75 c schematic diagram (typical channel) figure 1. v+ in x v gnd + s d v v+ 8888
dg201a/202 siliconix s-52880erev. e, 28-apr-97 3 specifications a test conditions unless otherwise specified v 15 v v 15v a suffix 55 to 125 c b, c, d suffix parameter symbol v+ = 15 v, v = 15v v in = 2.4 v, 0.8 v f temp b typ c min d max d min d max d unit analog switch analog signal range e v analog full 15 15 15 15 v drain source on resistance r ds( ) v d = 10 v i s =1ma room 115 175 175 drain - source on - resistance r ds(on) v d = 10 v , i s = 1 ma full 250 250 source off leakage current i s(off) v s = 14 v, v d = 14 v room full 0.02 1 100 1 100 5 100 5 100 drain off leakage current i d(off) v d = 14 v, v s = 14 v room full 0.02 1 100 1 100 5 100 5 100 na drain on leakage current i d(on) v s = v d = 14 v room full 0.15 1 200 1 200 5 200 5 200 digital control input current with ivlhih i inh v in = 2.4 v room full 0.0004 1 1 1 10 input voltage high i inh v in = 15 v room full 0.003 1 10 1 10 a input current with input voltage low i inl v in = 0 v room full 0.0004 1 10 1 10 dynamic characteristics turn-on time t on see switching time tcii room 480 600 600 ns turn-off time t off test circuit room 370 450 450 ns charge injection q c l = 1000 pf, v g = 0 v r g = 0 room 20 pc source-off capacitance c s(off) v s =0v v in =5v f=1mhz room 5 drain-off capacitance c d(off) v s = 0 v , v in = 5 v , f = 1 mhz room 5 p f channel on capacitance c d(on) + c s(on) v d = v s = 0 v, v in = 0 v f = 1 mhz room 16 pf off isolation oirr v in =5v r l =75 room 70 channel-to-channel crosstalk x talk v in = 5 v , r l = 75 v s = 2 v, f = 100 khz room 90 db power supply positive supply current i+ all channels on or off room 0.9 2 2 ma negative supply current i all channels on or off room 0.3 1 1 ma notes: a. refer to process option flowchart. b. room = 25 c, full = as determined by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data s heet. e. guaranteed by design, not subject to production test. f. v in = input voltage to perform proper function.
dg201a/202 4 siliconix s-52880erev. e, 28-apr-97 typical characteristics r ds(on) vs. v d and power supply voltage charge injection vs. analog voltage 15 70 60 50 40 30 20 10 0 10 20 30 10 5 0 5 10 15 v analog analog voltage (v) q (pc) q d q s r ds(on) () v d drain voltage (v) 25 15 5 5 15 25 300 250 200 150 100 50 t a = 25 c 5 v 8 v 10 v 12 v 15 v v+ = 15 v, v = 15 v t a = 25 c leakage vs. temperature r ds(on) vs. v d and temperature r ds(on) () v d drain voltage (v) temperature ( c) 15 10 5 0 5 10 15 100 na 55 35 15 5 25 45 65 85 105 125 10 na 1 na 100 pa 10 pa 1 pa 0.1 pa v+ = 15 v, v = 15 v v d = 14 v i s(off) , i d(off) , i d(on) 180 160 140 120 100 80 60 v+ = 15 v, v = 15 v 125 c 85 c 25 c 0 c 40 c 55 c i , i sd insertion loss vs. frequency supply current vs. switching frequency i+, i (ma) loss (db) f frequency (hz) f frequency (hz) 6 4 2 0 2 4 6 1 k 10 k 100 k 1 m i i + v+ = 15 v v = 15 v 1 k 10 k 100 k 1 m 10 m v+ = 15 v v = 15 v ref. 0.0 dbm see figures 3 and 4 r l = 50 1 m 1 k 2.0 0.0 2.0 4.0 6.0
dg201a/202 siliconix s-52880erev. e, 28-apr-97 5 typical characteristics (cont'd) leakage current vs. analog voltage crosstalk and off isolation vs. frequency (pa) i , i sd , iso (db) x talk f frequency (hz) v d or v s drain or source voltage (v) 10 20 15 10 5 0 5 10 15 20 8 6 4 2 0 2 4 6 8 10 v+ = 15 v v = 15 v t a = 25 c for i d(off) , v s = v d for i s(off) , v d = v s 10 k 100 k 1 m 10 m 0 20 40 60 80 100 120 140 160 v+ = 15 v v = 15 v ref. 0 dbm r l = 50 off isolation crosstalk i s(off) , i d(off) i d(on) (ns) t on ,t off (ns) t on ,t off 1000 900 800 700 600 500 400 300 200 100 switching time vs. power supply voltage switching time vs. temperature temperature ( c) v+ positive supply (v) 55 35 15 5 25 45 65 85 105 125 1000 10 12 14 16 18 20 22 900 800 700 600 500 400 300 200 100 v+ = 15 v v = 15 v v s = 2 v t on t off t on t off see figures 3 and 4
dg201a/202 6 siliconix s-52880erev. e, 28-apr-97 test circuits figure 2. switching time figure 3. off isolation v o is the steady state output with switch on. feedthrough via gate capacitance may result in spikes at leading and trailing edge of output waveform. 50% 0 v 3 v t off t on v o v s t r <20 ns t f <20 ns logic input switch input switch output 90% c l 35 p f r l 1 k v o = v s r l + r ds(on) r l v s = +2 v v o v v+ in s d 3 v 15 v gnd +15 v s in r l d r g = 50 v s v in 0v, 2.4 v off isolation = 20 log v s v o v+ 15 v gnd v c c +15 v in 1 0v, 2.4 v v o +15 v 15 v gnd r l v+ v nc x talk isolation = 20 log c v s c v o 0v, 2.4 v 50 v s s 1 in 2 s 2 r g = 50 d 1 d 2 c = rf bypass figure 4. channel-to-channel crosstalk figure 5. charge injection c l 1000 pf v g 3 v d v+ v r g 15 v gnd in s v o +15 v v o v o in x on on off v o = measured voltage error due to charge injection the charge injection in coulombs is q = c l x v o
dg201a/202 siliconix s-52880erev. e, 28-apr-97 7 application hints a v+ positive supply voltage (v) v negative supply voltage (v) v in logic input voltage v inh(min) /v inl(max) (v) v s or v d analog voltage range (v) 15 10 12 8 b 15 12 10 8 2.4/0.8 2.4/0.8 2.2/0.6 2.0/0.5 15 to 15 12 to 12 10 to 10 8 to 8 notes: a. application hints are for design aid only, not guaranteed and not subject to production testing. b. operation below 8 v is not recommended. applications figure 6. sample-and-hold lm101a +15 v 15 v 30 pf 15 v 15 v v+ v dg201a 50 pf 1000 pf j202 j500 j507 +15 v 2n4400 15 v v in v ou t 1 k 200 5 m 5.1 m acquisition time = 25 s aperature time = 1 s sample to hold offset = 5 mv droop rate = 5 mv/s logic input low = sample high = hold +
dg201a/202 8 siliconix s-52880erev. e, 28-apr-97 applications (cont'd) f c1 f c2 f c3 ttl control 150 pf 1500 pf +15 v dg201a gnd 30 pf lm101a +15 v 15 v frequency hz 1 10 100 1 k 10 k 100 k 1 m 40 0 160 120 80 voltage gain db f c4 select f c3 select f c2 select f c1 select r 1 = 10 k r 2 = 10 k r 3 = 1 m v out v 1 v c 4 c 3 c 2 c 1 f l1 f c4 f l2 f l3 f l4 a l (voltage gain below break frequency) = = 100 (40 db) r 3 r 1 f c (break frequency) = 1 2 r 3 c x 1 2 r 1 c x f l (unity gain frequency) = max attenuation = r ds(on) 10 k 40 db 0.015 f 0.015 f figure 7. active low pass filter with digitally selected break frequency 15 v + figure 8. a precision amplifier with digitally programable input and gains gain = gain 1 (x1) gain 2 (x10) gain 3 (x100) gain 4 (x1000) 15 v +15 v 15 v gnd dg200a 30 pf +15 v +15 v 15 v dg202 logic high = switch on + lm101a r f + r g r g v in1 v in2 ch 1 ch 2 r f1 18 k r f1 9.9 k r f1 100 r g3 100 r g2 100 r g1 2 k v+ v gnd v
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